This allows HyperLynx to accurately model the adaptive timing capabilities of modern DDR controllers. CA / CS adjustments at either the class level or individual bit level. HyperLynx VX.2.12 also has the ability to adjust controller output timing for Command/Address signals to improve DRAM timing margins. This allows system operating to be measured in compliance with the DDR5 spec. This accurately models rise/fall asymmetry, works with AMI models & Tx/Rx jitter specs, runs simulations in seconds, works with crosstalk analysis, and produces eyes plot with probabilities shown in color. New in VX.2.12 is the ability to simulate and plot DDR5 eye diagrams down to a probability of 1e-16 in both batch and interactive simulations. Hyperlynx offers full workflows for both pre-layout design exploration and post-route verification of DDR-based interfaces. Power Delivery Network (PDN) design & verification.In VX.2.12 improvements have been made across the following areas: The new VX.2.12 release of HyperLynx delivers state of the art simulation capabilities to mainstream designers by combining advanced modeling and simulation techniques with automated workflows that guide users through analysis step by step.

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